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Senior Analog Design Engineer/ Manager
DATE OF EXPIRY 2012-02-22
 
Location: Hsinchu or Taipei
 
E-MAIL:
 

This position is for a Senior Analog Design Engineer/Manager to co-lead an Analog Design Team for the development of high speed serial interfaces for multi-Gbps and 10Gbps applications from spec to mass production.

• Proven track record in the complete life cycle of a high speed IO product from definition, design, tapeout, debug, testing, yield analysis, product qualification to mass production
• Expertise in high speed transceiver PHY design, including Tx/Rx, Equalization, PLL, DLL, clock distribution, CDR, SSC, etc
• Familiar with one or more major high speed I/O protocols, such as SATA2/3, Display Port, 1G Ethernet, PCI-E2/3, USB3, 10Gb Serdes, etc
• Extensive experience with high speed IO debug, lab characterization, compliance testing, and mass production issues
• Good knowledge of silicon process technology, devices, signal/power integrity
• Solid understanding of analog layout techniques, including matching, ESD, latch up, parasitic optimization and floor planning
• Familiar with system level modeling using Matlab, Simulink, Verilog, or Verilog-A/AMS
• Familiar with industry standard design software for schematic capture, simulation, layout and physical verification
• Proven track record of technical leadership and project execution management
• Experience working with AE/QA/production teams and customers
• Must speak and write in English

 
 
 
 
 
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